The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for storing data containing a function of correcting the error of at least one bit.
Some prior semiconductor memory devices include auxiliary saving bit lines which serve to replace fixed defective bit lines produced at manufacturing stages for thereby improving the yield of memory devices. The replacement of defective bits with rescue bits in such semiconductor memory devices is carried out by a circuit designed exclusively for the replacing operation, a laser device, or other suitable devices. With the conventional arrangement, while the fixed defective bits included during the fabrication steps can be remedied, no unfixed bit defects which could be created by the encounter with alpha rays or the like can be saved at all.
There have been developed various systems for correcting bit errors on LSI chips which contain semiconductor memory devices, utilizing the following techniques:
(1) Error correction on majority logic;
(2) On-chip encoding/decoding circuit using an error correcting code; and
(3) On-chip horizontal and vertical parity check system.
The technique (1) however requires a chip having an area which is about three times as large as the area of a chip with no error correction arrangement thereon. The expedient (2) necessitates an additional error correction circuit which is of a relatively large scale and will consume an increased amount of electric power. The system (3) needs a large number of check bits because of parity checking required on all of data bits for correcting the error of one bit, and hence takes an extended period of time for error correction and results in increased electric power consumption.